1. Field of the Invention
The present invention relates to a data transmission circuit and method for transmitting data. More specifically, the present invention shows a data transmission circuit and method for decreasing signal interference on a data bus.
2. Description of the Prior Art
Generally speaking, microprocessor systems processing large amounts of data with high speed all have more than one data processing unit. Some data processing units such as a memory are used to store data. Others such as a central processing unit are used to operate and process data. Moreover, data processing units are used to coordinate data exchange between other data processing units. For example, a north bridge chip on a motherboard of a computer system is used to coordinate data exchange among the central processing unit, the memory, a graphic accelerator, and a south bridge chip. To exchange data with other data processing units for completing the whole function of a microprocessor system, each data processing unit is connected via a data bus. Each data processing unit uses a data transmission circuit to electrically connect to the data bus to send or receive data on the data bus.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of two data processing units 14 and 16 exchanging data through a data bus 12 in a typical microprocessor system 10. The microprocessor system 10 comprises two data processing units 14 and 16. Two data transmission circuits 18 and 20 are installed within the respective data processing units 14 and 16, and are electrically connected to both ends of the data bus 12 to handle data exchanges between the data processing units 14 and 16.
Please refer to FIG. 2. FIG. 2 is a block diagram of a prior art data transmission circuit 22. The data transmission circuit 22 comprises an internal circuit 24, a register 28, an output circuit 32, and a control circuit 34. The internal circuit 24 is electrically connected to the register 28, the register 28 is electrically connected to the output circuit 32, and the output circuit 32 is electrically connected to the data bus 12. The control circuit 34 controls the operation of the whole data transmission circuit 22 and is electrically connected to the register 28 and the output circuit 32. The internal circuit 24 has a data output level 26 for providing data, and the register 28 has a D flip-flop 30 for temporarily storing data. A clock signal controlling the D flip-flop 30 is supplied by the control circuit 34. If data is requested to be sent on the data bus 12 from the data transmission circuit 22, the data is transmitted to the register 28 from the data output level 26 of the internal circuit 24 first. After being triggered by the clock signal, the D flip-flop 30 sequentially transmits data to the output circuit 32 from the internal circuit 24. Then, the output circuit 32 outputs the data on the data bus 12 to complete the task of the data transmission circuit 22 transmitting data to the data bus 12.
After the data is transmitted to the data bus 12, the control circuit 34 controls the output circuit 32 with a control signal to disconnect with the data bus 12 so that the data bus 12 is in a floating state. When the data bus 12 is in the floating state, the data transmission circuit 22 either waits for another data transmission circuit connected to the other end of the data bus 12 to transmit data, or readies to transmit data through the data bus 12. For all data transmission circuits electrically connected to the data bus 12, while the data bus 12 is in the floating state, a turn-around cycle can be supplied to prevent interference on the data bus 12 and prevent a phenomenon of signal contention. After the data transmission circuit finishes transmitting data, the output circuit 32 usually disconnects with the data bus for a period of time.
As mentioned above, closing the data bus 12 helps to coordinate the transmitting of data between each data transmission circuit. Nevertheless, there is still a delay period from when the control circuit 34 sends a control signal to when the output circuit 32 totally disconnects with the data bus 12. In this delay period, the data transmission circuit 22 still transmits data to the data bus 12 through the output circuit 32. If the content of the data bus is changed (such as from high-level to low-level, or low-level to high-level) during the delay period, and then disconnected, it can be seen as an impulse signal transmitting on the data bus under the floating state. To get a more detailed understanding, please refer to FIG. 3. FIG. 3 is a timing diagram signals on nodes A, B, D, T, E in the data transmission circuit 22 shown in FIG. 2. A horizontal axis in FIG. 3 represents time. A signal 40 is a waveform of the clock signal on node T, and the control circuit 34 uses the clock signal to control the D flip-flop 30. Signal 42 represents data transmitted to the D flip-flop 30 from the data output level 26. Data packets 50, 52, 54, 56 are data that will be transmitted to the data bus 12 from the data transmission circuit 22. The D flip-flop 30 is triggered by the rising edge of the clock signal, and the data packets 50, 52, 54, 56 are transmitted to the output circuit 32 and are represented as data packets 50a, 52a, 54a, 56a in signal 44 on node B. At this time, please note that the control circuit 34 also uses a control signal 46 (on node E) to control the output circuit 32. When data packets 50a, 52a, 54a, 56a are transmitted to the output circuit 32, the signal 46 remains at a high level. Therefore, the four packets of data can be transmitted to the data bus 12, as shown on signal 48 of node D on the data bus 12. Data packets 50b, 52b, 54b, 56b in the signal 48 respectively correspond to data packets 50a, 52a, 54a, 56a in the signal 44. After transmitting the four packets of data, the control circuit 34 then changes the control signal 46 to a low-level from a high-level. In this way, the output circuit 32 disconnects with the data bus 12. Please note that the signal 42 has a follow-up data packet 58 after data packet 56. The data packet 58 is data transmitted from the data output level 26 contiguously, but the data packet 58 is not transmitted with the data packets 50, 52, 54, 56. The data packet 58 is transmitted to the output circuit 32 by the D flip-flop 30 when triggered by the clock signal. This is the case with data packet 58a in the signal 44. If the control signal 46 is immediately pulled low at the point of 60, the data packet 58a will still be transmitted to the data bus 12 because of the delay period, as shown with the data packet 58b in the signal 48. In the delay period, the data bus 12 still receives a small piece of data packet 58b from the output circuit 32, as the marked area 62 in the signal 48. In the delay period time, if contents of the data packet 56b and the data packet 58b are different, the signal level on the data bus 12 will be changed. However, the signal level is not changed to a stable state and the data bus 12 has been totally disconnected so that the signal 48 in the area 62 is an impulse signal. Since the data bus 12 is disconnected and in a floating state, two ends of the data bus 12 are equivalent to an open state. The impulse signal will be reflected by both ends of the route and will be transmitted back and forth on the data bus 12 continuously. Once the data bus 12 reconnects to transmit data, the impulse signal will interfere with the normal data transmission on the data bus 12, and then the operation of the whole microprocessor system is affected.
To solve the problem of the impulse signal, one solution of the prior art method is to disconnect the data bus 12 earlier. Please refer to FIG. 4 of a timing diagram of each node. The legend of FIG. 4 is the same as that of FIG. 3. Signals 64, 66, 68, 70, 72 are respective signals on nodes T, A, B, E, D in the data transmission circuit in FIG. 2. Data packets 74, 76, 78, 80 in the signal 66 are four pieces of data that are transmitted to the data bus 12. To prevent generation of the impulse signal, the control circuit 34 controls the output circuit 32 to disconnect the data bus 12 by pulling the control signal low at the point of 82. Because the data packet 80a in the signal 68 (on node B) has not completed a cycle, this ensures that the data packet 84a following the data packet 80a is not transmitted to the data bus. However, this shortens the cycle of the data packet 80a. 
Another prior art method to prevent the impulse signal is described with FIG. 5. Please refer to FIG. 5 of a timing diagram of each node signal in another prior art method of preventing generation of the impulse signal. The legend of FIG. 5 is the same as those of FIG. 3 and FIG. 4. The horizontal axis is time, and signals 85, 86, 88, 90, 92 are respective signals on nodes T, A, B, E, D in FIG. 2. Data packets 94, 96, 98, 100 in the signal 86 are transmitted. In the prior art method, the control circuit 34 delays the time for sending the control signal 90 at the point of 102. After the last data packet 100a of the signal 88 (on node B) is transmitted, more than half the cycle time of the signal 85 is spent waiting. Then the control signal 102 controls the control circuit 32 to disconnect the data bus 12. This way allows data packet 104a to reach a stable state in a half cycle of the signal 85 and disconnect the data bus 12 to prevent the impulse signal from being generated. Since the data packet 104b in the signal 92 will not be transmitted, the prior art method will not affect the four packets of data (i.e. data packets 94b, 96b, 98b, 100b in the signal 92) and avoids generating the impulse signal. The key to the prior art method is that the data packet 104a reaches a stable state in the half cycle of the signal 85. If the data packet 104a cannot reach a stable state in the half cycle of the signal 85, the generation of impulse signal cannot be prevented. By improving the art, the operating frequency of each data processing unit in the microprocessor system 10 increases, and the cycle of the signal 85 becomes very short. Therefore, in high-speed microprocessor systems, the data 104a cannot reach a stable state in the half cycle of the signal 85, and the impulse signal is still generated.